This invention relates to an address arithmetic circuit of a memory unit utilized in a processing system of digitalized analogue signals.
With recent development of various techniques regarding digital processings, analogue signals which have been transmitted at a high fidelity are recently digitalized. A typical example of such analogue signals are voice or speech signals.
As techniques of digitalizing voice signals are known various techniques including bit rate reduction encoding systems including Adaptive Predictive Coding with Adaptive Bit Allocation (APC-AB), Adaptive Transform Coding (ATC), Adaptive Differential Pulse Code Modulation (ADPCM) and Sub-Band Coding (SBC), and analysis synthesizing System such as Line Spectrum Pair (LSP) and Partial Autocorrelations (PARCOR); an equalizer and an echo canceller.
The outline of such high grade waveform encoding systems is disclosed in a James, L. Flanagan et al paper entitled "Speech Coding", I.E.E.E. Transactions on communications, Vol. COM-27, No. 4. April 1979, pages 710 through 737 and the detail of this system is disclosed in a paper of Masaki Honda et al of the title Adaptive Bit Allocation Scheme in Predictive Coding of Speech" I.E.E.E. International Conference on Acoustics, Speech and Signal Processing, May 1982, pages 1672 through 1675. Regarding ATC, reference is made to a paper of Raine Zelinski et al, I.E.E.E. Transaction on Acoustics, Speech, and Signal Processing, Vol. ASSP-25, No. 4 August 1977, pages 299-309, while a PARCOR system is disclosed in U.S. Pat. No. 3,662,115. Regarding LSP (modified APC), reference is made to Fumitada Itakura et al paper entitles "A Hardware Implementation of a New Narrow to Medium Band Speech Coding, I.E.E.E. International Conference on Acoustics, Speech and Signal Processing, 1982, May pages 1964-1967.
In such processing systems of voice or speech signals, generally a voice signal is sampled and data of several hundreds of samples are processed as one frame unit. For effecting this processing the data are once stored in a memory unit under the arithmetic of a digital signal processor, and the data thus stored are accessed according to a specific algorithm determined by various speech processing systems for performing a necessary address arithmetic. In this case, for accessing the data stored in the memory unit (actually there is a look-up table in addition to the data) an accurate address arithmetic according to a predetermined algorithm is required.
Same examples of various speech processing systems are given in the following Table I which shows the relation between speech processing systems and address modes utilized thereby.
TABLE I ______________________________________ speech address mode processing cycle modulo bit reverse system increment (APC) (DFT, DCT) (FFT) ______________________________________ ACCURATE WAVEFORM ENCODING SYSTEM APC-AB indispens- predictive DFT or FFT for LSP able for coding analysis ordinary processing ATC indispens- predictive DCT is effected for or- able for coding thogonal transform, ordinary which is realized at high processing speed with FFT ADPCM indispens- predictive -- -- able for coding ordinary processing SBC indispens- predictive conversion of signal able for coding wareform into ordinary frequency region processing ANALYSIS SYNTHESIZING SYSTEM PARCOR indispens- -- -- -- able for ordinary processing LSP indispens- -- In LSP analysis able for DFT or FFT ordinary processing equalizer indispens- AP estimation of equalized able for adaptive waveform in FFT ordinary predication processing echo indispens- AP estimation of canceller able for adaptive echo property in FFT ordinary predication processing ______________________________________
In Table I, the increment includes processings of filtering auto-correlation, windowing etc. while addressing is executed by ordinary increase or decrease. In the cycle mode, the address is circulated with a predetermined period and this mode is used in the adaptive predictive coding (APC) processing.
In the modulo mode, a spectrum of respective sampling points are determined according to their dispersion signals and the processings include discrete. Fourier transform (DFT) processings and discrete cosine transform processings (DCT).
In the bit reverse mode in which the bit order of a data series is reversed, fast Fourier transformation (FFT) is used.
Anyhow, to execute digital processing of speech, signal processings of various modes are necessary. In the prior art, for executing processing of various modes independent address arithmetic circuits for executing respective mode processings have been provided so that address arithmetic circuits became bulky. For this reason, it has been extremely difficult to fabricate such address arithmetic circuit on a single chip large scale integration (LSI) for one digital signal processing. Following are prior references 1. U.S. Pat. No. 4,181,976 2. Japanese Laid Open Patent Specification No. 135629/1977. It was proposed to execute a complex address arithmetic for a memory unit by software utilizing a general purpose microprocessor or computer.
In such digital processing, however, it is impossible to use so-called parallee pipe line in which data calculation and address arithmetic are performed alternately, thus decreasing processing speed. When such address arithmetic is intended to be performed by software as above described, with present day technique, it is necessary to prepare a processor having an ultra high speed cycle time which is impossible or extremely difficult to realize.